SPOEC - Rationale

As feature sizes on VLSI chips are reduced and the processing density increases, so the problem of matching the internal power of the chip to the I/O level that it is capable of handling becomes more difficult. Inevitably the physical limit to the number of pins that can be connected to the chip becomes a severe constraint on increasing system performance. This proposal aims to develop and exploit techniques for creating multiple (free-space) optical connections distributed across the full area of the IC (rather than just the edges) so as to remove this bottleneck.

Fundamental physical calculations [1] show that a 50W electrical connection of cross-sectional area x² and length y has an upper limit to its aggregate data bandwidth of 2.25×10¹⁴ (x/y)² bs^-1 – independent of how it is configured (i.e. whether it is one or many transmission lines). Thus if, say, a 0.5mm width around a 1cm square chip is devoted to I/O (area ~18mm²) then for signals travelling 15cm the limit on the data capacity would be 80Gbits^-1 – e.g. 200 pins at 400Mbits^-1. In practice this theoretical upper limit is difficult to approach for two reasons: (i) the full connection area cannot be utilised with 100% efficiency, and (ii) line drive power becomes a problem. The latter factor has also been extensively studied [2], showing that optical links dissipate proportionally less power as the length-bandwidth product increases. Optical connections therefore provide a means of circumventing both the fundamental and practical limitations of electrical links.

If we consider a typical electrical bond pad on a chip it has dimensions ~100mm×100mm. Optical connections, on the other hand, require areas of ~10mm×10mm. Of course, multiple chip assemblies, based on small-area solder bump connections are possible using either the MCM approach or small-area vias to make electrical connections between stacked chips, but these techniques rely on close packing of the connected IC's. By contrast, once in the optical domain, signals can be sent long distances (through free-space or fibres) without degradation. In addition cross-talk can be avoided, removing the need for costly shielding. The issues that must be addressed are: how to interface efficiently silicon chips to optical I/O, and how to most effectively use this improved capability? In this project we propose to combine CMOS (or BiCMOS) IC's with III-V semiconductor optoelectronic interfaces to obtain aggregate communication bandwidths in the THz regime. We shall then explore how such hybrid devices can be used, by constructing a high-performance demonstration system.

Hybrid optoelectronic devices can be constructed using the solder-bump/flip-chip technique. This requires contact pads of only ~15mm diameter on the silicon IC to make the connections to the opto-chip. Consequently several thousand such connections, across the area of a 1cm² chip, will take up only 1% of the area, including drivers and receivers (these pads could even overlay active circuitry). With each optical link running at 200-300MHz this would give an aggregate I/O of about 1Tbits^-1 per chip – with no restriction on the connection distance. This builds on some earlier work carried out under the ESPRIT-OLIVES programme and recent work by the proposers, which has already demonstrated the feasibility of parallel optical interconnects with 200Gbits^-1 aggregate capacity per chip.

The ultimate potential of these techniques is particularly exciting as they can be scaled up in both the time and space domains. As clock-rates on silicon IC's push up to the GHz regime, so this can be matched by the optical interface devices. Combining, say, a 1GHz clock with a modest increase in the number of optical I/O channels, for example 10⁴ configured as a 100×100 array, would yield an aggregate data rate of 10Tbits^-1. The final performance will be set by power dissipation issues, but this will correspond to a much higher limit than would be imposed on any equivalent electrical interconnect.

To explore this considerable potential we propose to work on two aspects of this technology: (i) the hybrid chip integration – using CMOS or BiCMOS, with either InGaAs electro-absorption modulators or GaAlAs VCSELs, to demonstrate near THz aggregate I/O – and (ii) the construction of an optoelectronic crossbar switch, capable of exploiting such a hybrid chip to provide a wide-band non-blocking connection between multiple electronic nodes.

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Last Modified 08/04/03 11:48:35.